Description
MatX is hiring a full-time Silicon Verification Engineer to contribute to scalable verification methodology across blocks, subsystems, full-chip, and system levels. The role owns subsystem and chip-level verification execution, creates testbenches and tests, drives intermediate and sign-off reviews, and supports silicon milestones through design freeze and tapeout. Candidates need at least five years of silicon design-verification experience, end-to-end concept-to-tapeout experience, production experience with SystemVerilog, UVM, assertion-based verification, formal and simulated verification, and scripting in Python, C/C++, or similar languages. The position offers tiered US base salaries of $160,000–$275,000, $175,000–$$400,000, or $250,000–$600,000 plus equity, along with medical, dental, vision, retirement, and other benefits.
