Description
River AI is hiring exception design verification engineers to ensure the functional correctness of high-performance custom silicon. The role involves defining verification plans, building UVM-based test environments, developing constrained-random and coverage-driven tests, applying formal and emulation methods, debugging RTL failures, and automating regression flows. Candidates need a bachelor’s degree in electrical, computer, or computer science engineering and at least five years of industry experience, along with deep UVM and SystemVerilog expertise and experience verifying high-performance silicon. The position is based in Austin, Texas or Palo Alto, California, with an expected annual salary of $200,000 to $420,000 USD plus equity, visa sponsorship, and health, dental, vision, PTO, and relocation benefits.
