Description
Etched is hiring a Design Verification Engineer for its Interface IP DV team to own verification of hardware IP subsystems and interfaces such as PCIe, Ethernet, CPU, low-power peripherals, and sensors. The role involves developing UVM and SystemVerilog verification environments, validating functional correctness and performance across the hardware-software stack, collaborating with architecture, design, integration, and SoC DV teams, and driving coverage closure and sign-off. The position is based in Austin with regular collaboration in San Jose.
