Design Verification Engineer, Memory Controller at ARM

Compensation

$249,900 – $338,100/yr

Setup: Hybrid
Type: Full-time
Level: senior

Description

Arm is hiring a Design Verification Engineer for Arm System IP, focused on one or more functional units of the Memory Controller. The role partners with performance modeling, validation, and implementation teams to meet functional requirements and PPA goals, and involves building SystemVerilog/UVM testbenches, verification plans, test cases, coverage, and debugging RTL using simulation and debug tools. The position is hybrid, based at Arm, and offers a salary range of $249,900 to $338,100 per year.

Required Skills

SystemVerilog/UVM
Python or Perl
SystemVerilog Assertions
Microarchitecture
RTL debugging
Functional coverage

Additional Information

Minimum Education: Bachelor’s or Master’s degree in Computer Science or Electrical/Computer Engineering
Required Previous Experiences: 7+ years of experience in microprocessor, SoC, memory controller, and/or interconnect IP design and verification
Preferred Qualifications: Knowledge of DRAM specifications such as LPDDR4/5, DDR4/5, or HBM
Knowledge of bus protocols such as AMBA5 CHI, AMBA4 ACE, or AXI
Processor system knowledge and basic understanding of SoC systems and operating system software

About ARM

ARM

compute platformsCambridge, UK

Build the future of AI with Arm, with the most power-efficient, high-performance, and scalable compute platform. Trusted by top tech partners to drive innovation and unlock new possibilities.

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