Design Verification Engineer — Memory Subsystem at Qualcomm International Inc., Mexico Branch Office

Qualcomm is hiring a Design Verification Engineer for its memory subsystem verification team. The role covers the full verification lifecycle for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY-related logic, and other high-performance memory subsystem components. Responsibilities include developing verification strategies and plans, building UVM-based testbenches, creating assertions and coverage models, executing simulations, debugging failures, and driving functional, code, assertion, and coverage closure. The position requires a bachelor’s, master’s, or PhD degree in a relevant technical field and 2–10 years of ASIC, SoC, IP, or subsystem design verification experience, with a pay range of $159,600 to $239,400.