Design Verification Engineer — Memory Subsystem at Qualcomm International Inc., Mexico Branch Office

Qualcomm Canada ULC is hiring a Design Verification Engineer for its memory subsystem verification team. The role covers the full verification lifecycle for complex digital designs, including memory controllers, DDR/LPDDR/HBM interfaces, PHY-related logic, and other high-performance memory subsystem components. Responsibilities include developing verification strategies and plans, building UVM-based testbenches, executing simulations, debugging failures, driving coverage closure, and collaborating with design, architecture, modeling, firmware, and system validation teams. The position requires a relevant bachelor’s, master’s, or PhD degree and 2–10 years of ASIC, SoC, IP, or subsystem design verification experience, with a stated salary range of $108,000 to $158,000.