Description
Meta Reality Labs is hiring a Design Verification Engineer for its custom silicon team to ensure the functional correctness and quality of complex AR/VR chips. The role owns verification plans, develops constrained-random UVM testbenches, defines functional and code coverage, builds simulation and regression infrastructure, performs formal verification, debugs RTL issues, and prepares pre-silicon test content for hardware bring-up. The position requires a bachelor's degree and at least six years of digital design verification experience, including UVM, SystemVerilog or VHDL, coverage, RTL debugging, and test automation.
