Description
Astera Labs is hiring a Principal Design Verification Engineer in San Jose, California, to own functional verification of high-speed SerDes/PHY IP for rack-scale AI infrastructure. The role involves architecting UVM-based verification environments, driving coverage closure, validating PHY behavior against PCIe, UALink, UCIe, and Ethernet standards, collaborating with analog and digital design teams, and mentoring junior engineers. Candidates need a bachelor's degree in a relevant engineering field, at least five years of high-speed SerDes, PHY, or mixed-signal IP verification experience, and expert SystemVerilog/UVM proficiency. The salary range is $160,000 to $200,000, with possible discretionary bonus, incentives, and benefits.
