Description
The DFT Architect will define and govern next‑generation DFT architecture for Altera’s FPGA, SoC, processor, DSP, SERDES, IO, and multi‑die silicon platforms. The role owns DFT strategy, methodology, advanced test architectures, multi‑die integration, silicon debug, manufacturing test optimization, EDA tool strategy, and technical mentorship, while collaborating with architecture, RTL, physical design, validation, product engineering, and manufacturing teams. It requires a bachelor’s degree and extensive industry experience in DFT, silicon bring‑up, manufacturing test, automation, and technical leadership, with a regular Shift 1 assignment in Penang, Malaysia.
