Description
Intel is hiring an experienced DFT Design Engineer in Austin, Texas, to design, integrate, verify, and optimize Design for Test functionality for complex SoC and IP designs. The role covers RTL coding, scan, MBIST, BSCAN, timing closure, ATPG and manufacturing test-content generation, DFT architecture, IP/SoC integration, ATE bring-up, and post-silicon validation. Candidates need a relevant bachelor's degree, at least five years of DFT or semiconductor design experience, Tessent Shell and SSN methodology expertise, hands-on ATPG/scan/MBIST experience, and RTL skills in Verilog, VHDL, or SystemVerilog. The position is on-site and offers an annual US salary of $141,910 to $200,340.
