Description
Role focused on defect modeling and test methodology development for advanced process nodes and advanced packaging technologies, including top/block-level DFT insertion, scan compression, boundary scan, IEEE 1500 wrapper, ATPG, pattern simulation, DFT verification, timing debug, and collaboration with physical design to resolve timing issues. The engineer is expected to work independently from DFT specification through final pattern delivery and contribute to diagnosis and yield learning using commercial EDA tools and scripting.
