Description
itD is hiring a DFT (Design For Test) Lead to lead hardware DFT implementation and integration across the ASIC development lifecycle. The role covers scan, memory BIST, BISR, boundary scan, DFT simulation, ATPG, post-silicon debugging, test architecture, and production qualification, while providing technical leadership to engineering teams. The position is available in Carlsbad, California; Allentown, Pennsylvania; or U.S. remote, with Pacific Time business hours and a 14-month duration. It requires a bachelor's or master's degree in electrical or computer engineering and 8–10+ years of ASIC DFT experience, and offers medical, dental, vision, retirement, and other benefits.
