The DFT Engineer will design and implement testability structures for complex ASIC/SoC designs, including scan insertion, ATPG, fault coverage analysis, MBIST, LBIST, and JTAG implementations. The role collaborates with RTL design teams, analyzes coverage gaps, supports silicon bring-up and yield analysis, and uses Synopsys, Cadence, and Mentor DFT tools while coordinating with foundry and test teams on ATE pattern conversion.
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mise en réseauSanta Clara, CA, US10001+
We create the world’s fastest supercomputer and largest gaming platform.
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