Description
Annapurna Labs is hiring a DFT Engineer to own testability architectures and DFT logic for complex SoC designs. The role covers MBIST, JTAG/TAP, boundary scan, RTL coding and debugging, gate-level simulation, UVM-based verification, coverage-driven testing, design reviews, sign-off, and tapeout preparation, with cross-functional collaboration across design, verification, physical design, and production/test teams. Required qualifications include RTL design experience with Verilog/SystemVerilog and chip design-flow and gate-level simulation experience; preferred qualifications include DFT implementation, EDA tools, UVM verification, scripting, and end-to-end chip development.
