Description
Annapurna Labs is hiring a DFT Engineer to own testability architectures and DFT logic for complex SoC designs. The role covers MBIST, JTAG/TAP, boundary scan, RTL coding and debugging, gate-level simulation, UVM-based verification, coverage-driven testing, design reviews, sign-off, and tapeout preparation, with cross-functional collaboration across design, verification, physical design, and production/test teams. Candidates need a bachelor's degree in Electrical Engineering, Computer Engineering, or Computer Science and at least two years of RTL design experience using Verilog or SystemVerilog.
