Description
The DFT Engineer will lead the complete digital design verification solution for a chip project, including DFT specifications, verification plans, SoC test interfaces, DFT architecture, testbenches, directed and constrained-random testing, failure debugging, gate-level simulation, coverage closure, and integration with synthesis, timing closure, STA, physical design, power, and logical analysis. The role also partners with Chip Architecture, DV, physical design, power, and test engineering teams to achieve first-tapeout success.
