DFT Engineer at Astera Labs

Astera Labs is hiring a Tech Lead Design Engineer to architect and deliver connectivity silicon for AI infrastructure. The role owns RTL design and implementation of complex blocks, develops synthesizable Verilog/SystemVerilog, leads design reviews and timing closure, partners with architecture, verification, DFT, and physical design teams, and mentors junior engineers. Candidates need a bachelor's degree in electrical or computer engineering, at least five years of digital design experience including a full chip from specification to tapeout, and strong proficiency in RTL, synthesis, timing closure, CDC, lint, and high-speed serial interfaces. The salary range is $133,200 to $185,000, with possible discretionary bonus, incentives, and benefits.