DFT Engineer at Google

Seniority in posting: Mid

Compensation

$163,000 – $236,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: mid
Posted: Aug 14, 2026

Description

Google is hiring a DFT Engineer to develop and deploy advanced design-for-test methodologies for TPU and other SoC and IP designs. The role covers DFT architecture, test strategies, scan, MBIST, JTAG, iJTAG, ATPG, diagnostic databases, silicon bring-up, debug, and yield improvement. Candidates need a bachelor's degree in a relevant engineering or computer science field and at least five years of DFT experience for SoCs; the listed compensation is $163,000–$236,000 USD plus a 15% bonus target, equity, and benefits.

Required Skills

DFT architecture
MBIST
JTAG
ATPG
Silicon bring-up
Debug
Yield
EDA tools

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Required Previous Experiences: 5 years of DFT architecture, implementation, and verification for SoCs
Experience in silicon bring-up, debug, or validation of DFT features
Experience with industry-standard test methodologies and platforms such as ATE, MBIST, JTAG, or System Level Test
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
10 years of DFT architecture, implementation, and verification for SoCs
Experience with various fault models
Experience in DFT flow, IP integration, and interaction with synthesis and verification flows
Experience with industry-leading EDA tools for DFT
Knowledge of test standards and test data formats