DFT Engineer at Kandou

Department: RnDSeniority in posting: Mid-level

Language

Location: St-Sulpice VD, Vaud
Type: Full-time
Level: mid
Posted: Jun 30, 2026

Description

Kandou is hiring a mid-level DFT Engineer for a 100% employment arrangement based in Lausanne, Switzerland or the United Kingdom. The role focuses on hierarchical MBIST and scan insertion, BSD implementation, ATPG pattern generation, coverage analysis, timing-based pattern simulation, IJTAG functional pattern development, test and production debugging, and silicon debugging. Candidates need at least five years of DFT experience, IJTAG and EDA tool experience, knowledge of System Verilog, and a bachelor's degree in a relevant engineering discipline.

Required Skills

MBIST
Scan insertion
ATPG
Coverage analysis
IJTAG
Timing constraints
System Verilog
EDA tools
Silicon debugging

Additional Information

Minimum Education: Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering, or an equivalent or higher qualification
Required Previous Experiences: At least 5 years of DFT experience, including implementation, test pattern development, and simulation
Experience contributing DFT solutions to complex designs
Experience with IJTAG methodologies
Experience with hierarchical MBIST, scan insertion, and scan compression methodologies
Experience with ATPG pattern generation, fault coverage analysis, and convergence to high coverage metrics
Experience with industry-standard EDA tools for DFT, timing, and simulation