Description
The role is responsible for implementing and verifying scan, MBIST, and boundary scan solutions for complex SoC designs, performing scan insertion and DFT DRC checks, analyzing fault coverage, developing ATPG patterns, and maintaining DFT automation flows. It also supports silicon bring-up, diagnosis, and yield improvement. The position requires a bachelor's or master's degree in a relevant engineering field, 1–3 years of VLSI, DFT, or semiconductor engineering experience, and proficiency in Verilog, VHDL, and scripting languages.
