Description
Etched is hiring a DFT Intern to review and refine DFT flow automation for chip-level regression on Caelius, contribute to DFT verification including MBIST, Scan, BSCAN, and SSN simulations, and develop flows for various ATPG fault models. The role works across frontend and backend design teams and is available for Summer '26, Fall '26, Spring '27, and Summer '27. It is a 12-week paid internship based in San Jose, California, with housing support and daily meals, and requires progress toward a degree in electrical, computer, or a related engineering field along with familiarity with hardware description languages, ASIC or SoC design, digital logic, ASIC design flow, and scripting.
