Description
The DFT Manager will lead and technically guide a high-performing DFT team across ASIC engagements, define chip-level testing plans involving Scan, MBIST, and IO/IP tests, collaborate with physical design, verification, and manufacturing teams on DFT architectures, and work with Automated Test Equipment post-silicon to achieve test coverage, resolve root-cause failures, and improve manufacturing yield. The role requires proficiency with Siemens Tessent, Synopsys TestMAX, and SpyGlass DFT, and a bachelor's degree with 12+ years of related experience or a master's degree with 10+ years of related experience.
