Description
Annapurna Labs is offering a three-month Design for Testability (DFT) training program for chip-design engineers. The program covers DFT architecture and strategy, testability design, physical implementation, verification and sign-off, and silicon bring-up and failure analysis. Applicants need a B.Sc. in Electrical or Computer Engineering, demonstrated academic performance, and must be curious graduates or students in their eighth semester willing to work full time; prior chip-design, DFT, or design-verification experience, Verilog and System Verilog knowledge, UVM familiarity, and scripting skills are preferred.
