Digital Design Engineer at Analog Devices, Inc.

Setup: Hybrid
Type: Full-time

Description

Analog Devices, Inc. is seeking a P3 Digital Design Engineer to join their Joint Development Team (JDT). This role involves contributing to RTL design, subsystem implementation, and mixed-signal integration of digital logic blocks. The engineer will write RTL for digital blocks, perform lint and CDC analysis, assist in writing functional test cases and UVM components, and collaborate with DV engineers for coverage closure and bug resolution. They will also support AMS co-simulation and integration with analog blocks, and work with physical design teams on synthesis and timing.

Required Skills

RTL design
subsystem implementation
mixed-signal integration
Write RTL for digital blocks based on specifications.
Perform lint, CDC analysis, and support DFT integration.
Assist in writing functional testcases and simple UVM components.
Collaborate with DV engineers for coverage closure and bug resolution.
Support AMS co‑simulation and integration with analog blocks.
Work with physical design teams on synthesis and timing.

Additional Information

Minimum Education: BS or MS in ECE, EE, CpE, or equivalent.
Required Previous Experiences: 2–5 years digital design experience, or strong NCG background.
Preferred Qualifications: Proficiency in SystemVerilog/Verilog; familiarity with UVM preferred.
Experience with scripting languages (Python/Perl/TCL).
Basic understanding of AMS modeling and mixed‑signal flows is a plus.