Description
Fortaegis is hiring a Digital Design Engineer to architect, develop, and integrate RTL and IP for FPGA and ASIC-based semiconductor products. The role covers RTL design, custom and third-party IP development, SoC and FPGA integration, synthesis and implementation, timing closure, power and area optimization, verification support, and coordination with architecture, hardware, software, and firmware teams. Candidates need at least five years of digital design and RTL experience, advanced SystemVerilog or Verilog knowledge, and familiarity with EDA tools, interfaces, verification methodologies, and scripting.
