Digital Design Manager at Astera Labs

Astera Labs is hiring a Digital Design Test Architect to lead day-to-day DFT architecture and execution for high-speed PCIe and Ethernet signal-conditioning products. The role owns test-access, coverage, observability, diagnostics, scan, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, SerDes BIST, tape-out readiness, yield learning, failure analysis, and production test approaches, while partnering with design, physical design, packaging, manufacturing, and test teams. It requires a bachelor’s degree in a relevant engineering field and 10–15 years of digital design or semiconductor design and test experience, with a salary range of CAD $198,000 to CAD $220,000.