Description
Synopsys is hiring a Senior ASIC Digital Design Engineer to own and deliver high-quality RTL for complex PCIe IP. The role involves implementing micro-architecture and design specifications, debugging in simulation and other verification environments, contributing to protocol discussions, maintaining RTL coding standards, collaborating with verification and physical design, and supporting synthesis, timing, and low-power feedback. Candidates need a BSEE with 5+ years of relevant experience or an MSEE with 3+ years, hands-on ASIC RTL design in SystemVerilog, and experience with at least one high-speed or on-chip interconnect protocol.
