Digital Design Verification Engineer at Altera

Altera is hiring an FPGA Verification Engineer to develop and maintain SystemVerilog/UVM verification environments for SerDes and PHY blocks. The role involves writing testbenches, functional coverage models, and assertions; running simulations; debugging RTL and testbench issues; and collaborating with design, architecture, and analog teams. It is intended for an early-career engineer with 0–5 years of digital design or verification experience, a relevant bachelor's degree, and strong digital design fundamentals. The position is based in Iași, Romania and is remote.