Digital Design Verification Engineer at E-Space

E-Space is hiring a full-time Digital Design Verification Engineer to verify custom ASICs for satellite and wireless telephony. The role requires strong Verilog and SystemVerilog skills, UVM verification experience, C/C++ and scripting abilities, RTL debugging, test-plan contribution, and block-level verification leadership. Candidates should have at least six years of semiconductor design verification experience, with LEO satellite component development experience preferred. The position is based in Saratoga and offers a target base salary of $120,000 to $220,000 annually.