Digital Design Verification Engineering Intern at Synopsys

Synopsys is hiring a full-time Digital Design Verification Engineering Intern in Mississauga, Ontario, Canada. The intern will verify Backplane Ethernet, PCIe, SATA, USB, and MIPI SERDES products by developing UVM and directed testbenches, functional coverage, assertions, RTL and gate-level debugging, code coverage, and bug tracking. The internship lasts 16 months, follows a hybrid model, and starts in May 2027. Applicants should be pursuing a bachelor's degree in a relevant engineering discipline, have prior co-op or internship experience, and demonstrate knowledge of Verilog or SystemVerilog, scripting, Unix/Linux, and digital design verification.