Synopsys is hiring a Digital Design Verification Intern to join its IP Group in Mississauga, Ontario. The role involves defining verification test plans, writing constrained-random SystemVerilog testbenches using UVM, creating assertions, debugging RTL and gate-level simulation failures, and performing functional and code coverage analysis. The internship is a full-time, 16-month co-op program with a hybrid work model and a start date of May 2027.
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