Digital Silicon Design Engineer at Google

Seniority in posting: Mid

Language

Location: Haifa, Haifa District · Tel Aviv, Tel-Aviv District
Level: mid
Posted: Aug 27, 2026

Description

Google is hiring a Digital Silicon Design Engineer to define block-level designs and perform RTL coding, simulation, synthesis, timing and power closure, verification, and sign-off activities for custom silicon. The role requires a bachelor's degree in a relevant engineering or computer science field and at least four years of digital logic and RTL design experience, along with synthesis, low-power, SoC/IP, and design-quality-tool experience. Preferred qualifications include advanced degrees, formal verification, FPGA and emulation experience, and knowledge of DDR or HBM. The position is based in Haifa or Tel Aviv, Israel, and typically requires in-person interviews.

Required Skills

RTL coding
Verilog
SystemVerilog
Logic synthesis
Timing closure
SoC architecture
Formal verification
FPGA

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Required Previous Experiences: 4 years of experience with digital logic design principles, RTL design concepts, and Verilog or SystemVerilog.
Experience with logic synthesis, RTL optimization, performance and power, and low-power design techniques.
Experience with design sign-off and quality tools such as Lint and CDC.
Experience with SoC or IP architecture.
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture.
Knowledge of high-performance and low-power design, assertion-based formal verification, FPGA and emulation platforms, and SoC architecture.
Knowledge of DDR, LPDDR, or HBM.
Excellent problem-solving and debugging skills.