Description
The role develops and maintains UVM-based verification environments for semiconductor IPs, including SystemVerilog testbenches, constrained-random stimulus, scoreboards, monitors, coverage models, regression infrastructure, and FPGA-based pre-silicon validation. It also supports RTL and gate-level simulation, verification automation, and functional and code coverage closure. The position requires a bachelor’s degree in Electronics or Computer Engineering, 0–3 years of experience developing SystemVerilog-based verification environments, strong knowledge of Verilog and SystemVerilog, UVM proficiency, and fluency in English.
