Description
Synopsys is hiring a senior mixed-signal PHY verification engineer to develop and execute verification plans, perform RTL and gate-level simulations, build functional tests, analyze power and waveforms, debug failures, and collaborate with design and integration teams on high-speed PHY IP. The role requires at least five years of ASIC RTL verification experience, strong SystemVerilog and UVM skills, SDF-annotated gate-level simulation expertise, and knowledge of power-analysis tools; DDR, HBM, or UCIe PHY knowledge is a plus. The position offers health, wellness, and financial benefits, with salary details provided by the recruiter.
