Director, Package Design Engineering at RenesasElectronics

Seniority in posting: director

Compensation

$230,000 – $260,000/yr

Setup: Hybrid
Location: San Jose, California
Type: Full-time
Level: senior
Posted: Sep 26, 2026

Description

Renesas is hiring a senior Packaging Development Engineer to lead new package development, product qualification, technology roadmaps, R&D budgets, and customer adoption programs for AI and datacenter power packaging. The role focuses on power SiP and module technologies, WBG substrates, advanced interconnects, OSAT and contract-manufacturer qualification, process optimization, reliability, production ramp-up, quality controls, and customer issue resolution. Candidates need a relevant engineering degree, 15–20 years of packaging development experience, and expertise in power SiP, wafer-level and flip-chip packaging, assembly, qualification, SPC, and statistical analysis. The expected annual pay range is $230,000–$260,000, with bonus opportunities.

Required Skills

Package development
Power packaging
Wafer-level packaging
SPC
Statistical analysis
Wire bonding
Communication

Additional Information

Minimum Education: Doctorate, master’s, or bachelor’s degree in Physics, Chemistry, Mechanical, Electrical, or Materials Engineering
Required Previous Experiences: 15–20 years of relevant packaging development experience, emphasizing power SiP/module, wafer-level, and flip-chip packaging
Preferred Qualifications: Knowledge of wafer-level, flip-chip, multi-chip module, and power devices
Knowledge of wire-bonding and multi-chip module technologies
Translation Company Name: Renesas Electronics