Description
Astera Labs is hiring a Director, Physical Design to lead and grow its Physical Design function in Hyderabad. The role oversees the full-chip physical implementation of complex, high-speed connectivity ASICs and SoCs, including floor planning, placement, clock tree synthesis, routing, timing closure, power integrity, physical verification, and tapeout delivery. The Director will build and mentor a high-performing team, establish design methodology and EDA flows, drive automation, and collaborate with global RTL, DV, DFT, packaging, and architecture teams. The position requires a bachelor’s or master’s degree in a relevant field, at least 18 years of ASIC physical design experience including 5 years in leadership, and a proven record of successful tapeouts at advanced nodes.
