Description
Micron Technology is hiring a DRAM Layout Engineer to translate schematics into layouts for DRAM fabrication reticules, develop and verify IP layouts, perform LVS/DRC/EM and other physical verification activities, optimize routing and design rules, and lead layout development for complex digital and analog circuits. The role requires a BE/BTech or MTech in electronic or VLSI engineering, at least three years of advanced CMOS layout experience, Cadence Virtuoso and Mentor Calibre expertise, and the ability to collaborate with global engineering teams.
