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DRAM Layout engineer (Intern) at Micron

Department: DTPG

Language
Setup
On-site
Location
Tlaquepaque, Jalisco
Level
entry
Posted

Description

Micron is hiring a Semiconductor Physical Design Engineer to develop high-quality physical layouts for cutting-edge DRAM products. The role collaborates with design, layout, and verification teams to design and verify analog and digital layouts, use EDA tools such as Cadence and Calibre, floor-plan and design layouts, apply automated layout techniques, and follow verification protocols. Candidates must be pursuing a bachelor's degree in a relevant engineering or nanotechnology field, have coursework or projects related to microelectronics or VLSI, and understand CMOS technology and layout design principles.

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