Description
The role is responsible for developing and executing verification plans for IP, subsystem, and SoC designs; building UVM and SystemVerilog verification environments; creating testcases, stimulus generators, checkers, scoreboards, and coverage models; performing functional, code, assertion, and toggle coverage closure; debugging SystemVerilog Assertions; collaborating with RTL designers and validation teams; analyzing simulation results; verifying protocols such as AXI, PCIe, USB, Ethernet, DDR, and MIPI; managing regression and sign-off; and contributing to reusable verification IP and emulation or FPGA-based verification.
