Description
The Lead Engineer will lead and drive subsystem, SOC, and IP design verification for an ARM-based SoC. Responsibilities include developing and debugging System Verilog/UVM testbenches, defining test plans and coverage metrics, executing directed, random, and constrained-random tests, and resolving simulation failures across IP, interconnects, subsystems, and the top level. The role requires at least five years of hands-on IP/SOC verification experience, strong SOC architecture knowledge, familiarity with VCS or Xcelium, scripting ability, and experience with at least two high-speed interfaces.
