Description
The GPU Top Level Physical Design engineer will collaborate with the frontend team to translate RTL into physical design, drive physical design methodologies and guidelines, and serve as the focal point for top-level place-and-route integration. The role requires hands-on experience with large-chip integration, ASIC physical design, and cross-functional coordination, with responsibilities spanning floorplanning, clock and power distribution, global and I/O planning, hard IP integration, and physical design verification.
