Engineer II-Design at Microchip - USA

Location: Allentown, Pennsylvania
Level: mid
Posted: Jul 14, 2026

Description

Microchip Technology Inc. is hiring an RTL/ASIC Design Engineer to design, simulate, and verify RTL-based blocks for its SoC devices. The role covers module design, performance analysis, RTL implementation, synthesis, formal and RTL/gate-level simulation, timing verification, and support for test-chip and emulation-porting. Candidates need 2–5 years of RTL design experience, a bachelor’s degree in a relevant engineering or computer science field, SystemVerilog proficiency, and experience with RTL design, verification, synthesis, and static timing analysis tools.

Required Skills

RTL Design
SystemVerilog
Synthesis
Formal Verification
Static Timing Analysis
FPGA Design
TCL/Perl/Python
Linux

Additional Information

Minimum Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science
Required Previous Experiences: 2–5 years of RTL design experience for ASIC implementation
Experience with RTL design tools covering design entry, synthesis, formal verification, RTL/gate-level simulation, clocking analysis, and static timing analysis
Practical experience in RTL design, verification, synthesis, and formality
Ability to design complex state machines and data-path logic
Preferred Qualifications: Master’s degree in Electrical Engineering, Computer Engineering, or Computer Science
FPGA and ASIC SoC design experience
Laboratory experience for system-level validation
FPGA design and board implementation experience