Description
The Semiconductor Integrated Circuit Layout Engineer is responsible for cell layout, block-level layout, macro planning, and interconnect, with compact layout being essential. The role works under a designer’s supervision to maintain schedule and quality, requires a BS or MS in Electrical Engineering and 1–3 years of semiconductor integrated circuit layout development experience, and requires fluency in Unix and mainstream CAD layout tools. Vietnamese and English fluency are preferred, and the position may require 0–25% travel.
