Description
SiFive is hiring a Senior Physical Design Engineer to execute and optimize RTL-to-GDS implementation flows for high-performance CPU cores. The role owns medium-sized CPU sub-blocks from synthesis through GDS sign-off, drives block-level PPA closure, uses ML-enhanced design tools, troubleshoots flow and tool issues, and develops Tcl/Python automation. Candidates need at least two years of physical design or methodology experience, FinFET node knowledge, Synopsys digital implementation expertise, and strong Tcl/Python skills.
