Engineer II, Physical Design - Cores at SiFive

Location: Bengaluru, Karnataka
Type: Full-time
Level: entry
Posted: Sep 3, 2026

Description

SiFive is hiring an entry-level Physical Design Engineer to help build high-performance RISC-V CPUs by participating in the end-to-end ASIC physical design flow from RTL to GDSII. The role involves synthesis, place and route, timing closure, PPA analysis, cross-abstraction-layer co-design, and automation with Python, Tcl, or Bash. Candidates should have a bachelor’s or master’s degree in electrical or computer engineering, computer architecture knowledge, digital design and RTL skills, VLSI exposure, and scripting proficiency; the posting also considers new graduates with strong academic credentials.

Required Skills

Physical design
RTL
Place and route
Timing closure
Python
Tcl
Bash
Computer architecture
VLSI design

Additional Information

Minimum Education: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
Required Previous Experiences: 3+ years of experience
Academic coursework, projects, or internship experience related to VLSI design or ASIC flows
Preferred Qualifications: Excellent academic credentials
Work experience with physical design implementation

About SiFive

SiFive

RISC-V

SiFive delivers high-performance, scalable processor core IP solutions using the open RISC-V standard, with flexible customization and power efficiency. Its products include customizable scalar, vector, and matrix solutions, including scalable AI matrix engines for companies developing custom AI solutions and systems for edge IoT, consumer devices, autonomous vehicles, and data centers. SiFive IP powers over 2 billion devices worldwide and has achieved 400+ RISC-V design wins.