Description
Micron Technology is hiring a Senior Memory Layout Engineer-DPG-LPDDR to develop memory and storage solutions, with a focus on LPDDR memory architecture. The role involves bit-cell layout creation, pitch matching, row and column decoder development, memory array hierarchy, decode-path implementation, Cadence Virtuoso layout, Calibre DRC/LVS debugging and closure, device physics, transistor matching, well and substrate engineering, parasitic optimization, and EM/ESD reliability. The engineer will independently deliver layout blocks, support data-driven optimization and layout automation, and apply AI/ML knowledge to improve debug and correlation workflows. The posting requires a B. Tech/B. E. or M. Tech. in a relevant electronics or VLSI field and at least two years of memory and full-custom layout development experience.
