Description
Micron Technology is seeking a standard-cell layout engineer to design and maintain standard-cell layouts for new DRAM products, lead stdcells projects from specification through PPA-qualified library release, collaborate with DTCO, CMOS, and CAD teams, perform LVS/DRC/latchup verification, guide junior members, and develop automated flows and AI-assisted workflows. The role also requires project-management leadership, scheduling, delegation, and coordination with international colleagues.
