Description
Synopsys is hiring a Principal ASIC Digital Design Engineer (Verification) in Bengaluru to architect and implement scalable verification flows and infrastructure for digital IP and SoC products. The role requires 10+ years of IP or SoC verification experience, expertise with VCS, Verdi, VMS Execution Manager, Verdi Planner, and VIPs, and strong SystemVerilog, UVM, Tcl, and Python skills. The engineer will lead verification methodology standards, mentor engineers, manage technical initiatives, collaborate with EDA tool development teams, and improve verification quality and cycle time.
