Description
Synopsys is hiring a Principal Engineer / Architect for Digital Design Verification in Bengaluru, India. The role will architect and implement unified verification flows and scalable infrastructure for digital IP and SoC products using VCS, Verdi, VMS Execution Manager, Verdi Planner, and VIPs; establish verification methodologies; lead and mentor verification engineers; manage technical initiatives; and collaborate with EDA tool development teams. Candidates need more than 10 years of IP or SoC verification experience, deep expertise with the listed Synopsys tools, strong SystemVerilog, UVM, Tcl, and Python skills, and a bachelor's degree in a relevant engineering field.
