Description
The Ethernet Design Verification Engineer will verify high-speed Ethernet IP and subsystems before tapeout by developing UVM-based testbenches, writing protocol-level test cases, validating IEEE 802.3 compliance across speed grades, performing coverage analysis, debugging simulation failures, developing verification IP, supporting regression and continuous integration, and correlating simulation results with post-silicon validation. The role requires SystemVerilog, UVM, Ethernet protocol knowledge, verification IP development, simulator experience, and scripting skills, with 5–16 years of DV/verification experience and Ethernet protocol experience strongly preferred.
